Search - VHDL algorithm

[Other resource] 用VHDL实现布斯算法

Description: 这个例子是讲述用VHDL实现布斯算法，应该有点用，是我的研究生师哥给我的。-this case is about the use of VHDL Booth algorithm, should use a bit of my graduate students Shige to me.
Platform: | Size: 1897 | Author: 刘于 | Hits:

[Other resource] vhdldesign

Description: 浮点加法器的VHDL算法设计浮点加法器的VHDL算法设计-floating point adder VHDL algorithm design of the floating point adder VHDL Design Algorithm
Platform: | Size: 203178 | Author: yan | Hits:

[Compress-Decompress algrithms] lzw_soft

Description: lzw压缩解压算法源码-The soruce of LZW compression algorithm
Platform: | Size: 0 | Author: 站长 | Hits:

[Crack Hack] rom_des

Description: DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。-VHDL and VERILOG sourcecode and TESTBENCH of DES encrypting algorithm
Platform: | Size: 30720 | Author: | Hits:

[VHDL-FPGA-Verilog] vhdldesign

Description: 浮点加法器的VHDL算法设计浮点加法器的VHDL算法设计-floating point adder VHDL algorithm design of the floating point adder VHDL Design Algorithm
Platform: | Size: 202752 | Author: yan | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 伪随机序列发生器的vhdl算法设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）。 -Pseudo-random sequence generator algorithm VHDL design of a pseudo-random sequence generator, using the generation polynomial for the 1+ X ^ 3+ X ^ 7. RESET has a client request and the two control registers client to adjust the initial value (procedures set of four non-zero initial value optional).
Platform: | Size: 1024 | Author: 文成 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 用VHDL语言编写的一个乘法器校程序是基于BOOTH算法的 -VHDL language using a multiplier BOOTH school program is based on the algorithm
Platform: | Size: 1024 | Author: 杨天 | Hits:

[Algorithm] CORDIC

Description: cordic算法，包含所有的CORDIC的算法，与发表过的论文，与实现方案-CORDIC algorithm, contains all of the CORDIC algorithm, and published papers, and implementation of programs
Platform: | Size: 8102912 | Author: elisen | Hits:

[Algorithm] FFT(VHDL)

Description: 数字信号处理fft算法计算，用fpga开发，vhdl语言写成-Digital signal processing fft algorithm using FPGA development, vhdl language
Platform: | Size: 14336 | Author: 程钢 | Hits:

[VHDL-FPGA-Verilog] vhdl-Algorithm-Hard-wired-logic

Description: 大型数字系统设计中，vhdl中从算法到硬线逻辑实现的教程-Large-scale digital system design, vhdl from hard-wired logic algorithm to realize the Tutorial
Platform: | Size: 830464 | Author: 王辉 | Hits:

[VHDL-FPGA-Verilog] cordic

Description: vhdl语言编写的cordic算法，实现了cordic的流水线运算。-cordic language vhdl algorithm cordic the pipeline operator.
Platform: | Size: 1024 | Author: lmy | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: design of vhdl coding for genetic algorithm
Platform: | Size: 237568 | Author: ram kumar | Hits:

[Data structs] cordic

Description: cordic算法的VHDL实现，在FPGA下应用-cordic VHDL algorithm implemented in the FPGA application under
Platform: | Size: 48128 | Author: 范丹丹 | Hits:

[VHDL-FPGA-Verilog] RC5-VHDL

Description: RC5 encryption algorithm In VHDL
Platform: | Size: 10240 | Author: siavosh | Hits:

[matlab] matlab-genetic-algorithm

Description: matlab用法主要用于线性规划，非线性规划，解决优化问题，作出最合理的决策等遗传算法程序-matlab usage is mainly used for linear programming, nonlinear programming to solve optimization problems, make the most rational decision-making, genetic algorithm
Platform: | Size: 8192 | Author: 刘旭 | Hits:

[VHDL-FPGA-Verilog] RC6-block-cipher-using-VHDL

Description: VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped
Platform: | Size: 55296 | Author: waleed | Hits:

[VHDL-FPGA-Verilog] HASH-code-implementation-using-VHDL

Description: implementation for Secure Hash Algorithm 1 SHA-1 in vhdl language contain no test file.
Platform: | Size: 14336 | Author: waleed | Hits:

[VHDL-FPGA-Verilog] vhdl-implementation-of-huffman-algorithm

Description: VHDL implementation of HUFFMAN algorithm
Platform: | Size: 5120 | Author: anu | Hits:

[Other] VHDL.Programming.by.Example.4th.Ed

Description: 这是一本关于VHDL算法编程的国外经典教材，对于那些想要学习VHDL算法VHDL实现的会有很大帮助！-This is a book about VHDL programming of the classic teaching abroad, for those who want to learn VHDL implementation of the VHDL algorithm will be of great help!
Platform: | Size: 1786880 | Author: Kalman_li | Hits:

[File Format] vhdl

Description: 伪随机序列发生器的vhdl算法设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）--Design of VHDL algorithm for pseudo random sequence generator is a pseudorandom sequence generator, using the generating polynomial 1+X^3+X^7. RESET has a client request and the two control registers client to adjust the initial value (procedures set of four non- zero initial value optional)
Platform: | Size: 1304576 | Author: 沙爽 | Hits:

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[Other resource] 用VHDL实现布斯算法

[Other resource] vhdldesign

[Compress-Decompress algrithms] lzw_soft

[Crack Hack] rom_des

[VHDL-FPGA-Verilog] vhdldesign

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] vhdl

[Algorithm] CORDIC

[Algorithm] FFT(VHDL)

[VHDL-FPGA-Verilog] vhdl-Algorithm-Hard-wired-logic

[VHDL-FPGA-Verilog] cordic

[VHDL-FPGA-Verilog] vhdl

[Data structs] cordic

[VHDL-FPGA-Verilog] RC5-VHDL

[matlab] matlab-genetic-algorithm

[VHDL-FPGA-Verilog] RC6-block-cipher-using-VHDL

[VHDL-FPGA-Verilog] HASH-code-implementation-using-VHDL

[VHDL-FPGA-Verilog] vhdl-implementation-of-huffman-algorithm

[Other] VHDL.Programming.by.Example.4th.Ed

[File Format] vhdl

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